1. Technical Field
This is related to internal power-supply circuits having a reference-voltage generating unit in semiconductor integrated circuits.
2. Description of the Related Art
A semiconductor integrated circuit, for example, a DRAM, has an internal power-supply circuit for generating a internal power-supply step-down voltage from an externally supplied power-supply voltage Vdd, in order to achieve both high speed operation and low power consumption. The internal power-supply step-down voltage causes an internal circuit to operate. The internal power supply circuit also generates an internal power-supply step-up voltage and a bias voltage for current sources, which voltages are higher than the externally supplied power-supply voltage Vdd. It is required that internal voltages generated by the internal power-supply circuit, i.e., an internal power-supply step-up voltage, an internal power-supply step-down voltage, a bias voltage, and so on, have desired potentials. Accordingly, the internal power-supply circuit generates a desired reference voltage from the externally supplied power-supply voltage Vdd, and generates the internal voltages based on the reference voltage.
The internal power-supply step-down voltage is supplied to a peripheral circuit of the DRAM and is also supplied to a memory core having a memory cell array. The internal power-supply step-up voltage is supplied to the memory core. The current-source-bias voltage is supplied to current-source transistors of voltage-detection differential amplifier circuits and a delay circuit in the peripheral circuit to cause the current-source transistors to generate desired currents.
During power up, the internal power-supply circuit monitors the rising of the externally supplied power-supply voltage Vdd, and upon detecting the rising, the internal power-supply circuit starts a reference-voltage generating unit. After a reference voltage is generated, the internal power-supply circuit starts an internal-voltage generating unit that includes an internal power-supply step-down voltage generating circuit, an internal power-supply step-up voltage generating circuit, a current-source-bias generating circuit, and so on. Upon detecting the rising of all internal voltages and internal power-supply voltages, the internal power-supply circuit outputs a start signal indicating that the series of starting internal-power-supply operations has been completed. In response to the start signal, the internal circuit starts operation.
Since the above-described reference voltage is used as a reference voltage for the various internal power-supply voltages and the internal voltages, it is required that the reference voltage has a desired fixed level that is independent of the level of the externally supplied power-supply voltage Vdd. During a burn-in test, however, the potentials of the internal power-supply voltages are controlled so that they are higher than those for the normal operation to cause a defect in the integrated circuit to appear. Thus, it has been proposed that the reference voltage for the burn-in acceleration test is set to have a higher potential than that for the normal operation.
For example, Japanese laid-open patent publication No. 6-208791 discloses a technology in which a DRAM is provided with a first constant-voltage generating circuit for generating a first reference voltage that is independent of an external power-supply voltage and that is used for a normal operation and a second constant-voltage generating circuit for generating a second reference voltage that is dependent on the external power-supply voltage and that is used for a burn-in acceleration test.
Japanese laid-open patent publication No. 2004-55001 discloses a technology in which, during a burn-in test, a reference voltage for a burn-in test instead of a reference voltage used for a normal reading operation is applied to a memory device employing a TMR (tunneling magneto resistance) device. However, the burn-in test reference voltage is applied externally from a tester during the burn-in test.
Japanese laid-open patent publication No. 5-136680 discloses a technology in which a reference voltage during aging is set lower than a reference voltage of a current switch during a normal operation, for a level conversion circuit for a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuit with an ECL (emitter couple logic) interface. This publication is not directly related to the above-described burn-in test reference voltage.
The DRAM disclosed in Japanese laid-open patent publication No. 6-208791 described above is provided with the second constant-voltage generating circuit for generating the second reference voltage that is dependent on the external power-supply voltage and that is used for the burn-in acceleration test. Thus, by performing control to increase the potential of the external power-supply voltage during the burn-in acceleration test, it is possible to make the internal power-supply voltage in the cell array in a memory core to have a higher potential than that for the normal operation. This arrangement makes it possible to cause a defective portion to appear and makes it possible to detect a chip having a potential defect.